Monday, April 27, 2009

A Computer System Claim Not Within 101

Ex parte Jonathan E. Greene
Decided: April 24, 2009

Although this isn't the first time that a panel has held an apparatus was not within the scope of 101, this decision caught my attention because it deals with the "mathematical algorithm" exception.

Greene's application was generally directed to methods and an apparatus that improve on existing Fast Fourier Transform (FFT) calculations. The claim 60 provides further details of the improvement. Dependent claim 61 also adds to the discussion. Both claims are reproduced below. Sorry, claim 60 is a bit long.

Claim 60. A computer system for performing a fast Fourier transform on N ordered inputs in n stages comprising:
one or more vector processors configured as a non-final stage calculating means for repetitively performing in-place butterfly calculations for n-1 stages;

the one or more vector processors further configured as a final stage calculating means for performing a final stage of butterfly calculations including:

a first loop means for performing a portion of the final stage butterfly calculations, the first loop means performing a set of butterfly calculations, and storing butterfly calculation outputs in shuffled order in place of the selected inputs to result in a correct ordering of transform outputs; and

a second loop means for performing a remaining portion of the final stage butterfly calculations, the second loop means performing two sets of butterfly calculations, and storing butterfly calculation outputs from a first one of the two sets of butterfly calculations in shuffled order in place of the inputs selected for a second one of the two sets of butterfly calculations and storing butterfly calculation outputs from the second one of the two sets of butterfly calculations in shuffled order in place of the inputs selected for the first one of the two sets of butterfly calculations to result in a correct ordering of transform outputs,

wherein the final stage calculating means performs all butterfly calculations as radix-4 butterflies having four inputs and four outputs, wherein N is a power of two, and wherein the non-final stage calculating means performs a first stage of radix-8 butterfly calculations followed by n-2 stages of radix-4 butterfly calculations,

wherein the computer system produces the correct ordering of transform outputs with no need to perform an additional bit-reversal ordering pass.

Claim 61. The computer system of claim 60, wherein the non-final and final stage calculating means include a four-fold single instruction multiple data (SIMD) processor for performing four radix-4 butterfly calculations at a time.

The Examiner rejected these claims under 101 using pre-Bilski analysis. Throughout the prosecution, the applicant argued that the claim was patent eligible because it was directed to a machine. For example, he argued that claim 60 “defines a computer system that includes specific hardware structures, namely, vector processors. Moreover, it defines those structures in connection with means, (implemented in software) namely, the first loop means, second loop means, non-final stage calculating means, and final stage calculating means that are implemented, in the specification, in software."

It its analysis, the panel recognized that these claims were distinguishable from the method or process claims considered by the court in Bilski. The panel found that the preamble of independent claim 60 positively recites a computer system which is supported in the language found in the body of the claim. As such, the panel determined the claimed “computer system” was an apparatus which executes a software program.

With that in mind, the panel phrased the question before them as: "whether the 'mathematical algorithm' exception applies to an apparatus claim where the practical result of granting such a claim would preempt substantially all uses of a fundamental principle."

As you can guess, the Board found the claim did not fall withing the scope of 101.

The Board that these claims merely implement an optimized Fast Fourier Transform on a conventional computer system that includes one or more conventional vector processors. As claimed, we find the transform output results of the FFT calculation are not used for any practical purpose or inventive application whatsoever.

Further, the Board reasoned that without the recited conventional hardware elements, Appellant’s claim would be non-statutory under 35 U.S.C. § 101 as being directed to an abstract idea and/or a fundamental principal (i.e., a mathematical algorithm). Therefore, the question that remains is whether drafting an invention in a different statutory category (i.e., as a conventional apparatus or machine) is all that is necessary to overcome a § 101 rejection of a pure mathematical algorithm, particularly in view of the Federal Circuit’s recent discussion of Benson, stating that a computer-implemented method is not patent-eligible if the mathematical algorithm has no other use than operating on a digital computer and would preempt the fundamental principle since all uses of the algorithm are still covered by the claim.

In the end, the Board stated that merely adding a nominal recitation of conventional computer hardware in a claim otherwise directed to a pure mathematical algorithm is merely an exercise in claim drafting that cannot, by itself, render the claim statutory. The panel also said that it was their reasoned view that to hold otherwise would exalt form over substance and the practical effect would be a patent on the mathematical algorithm itself. The Board also said that the purpose of 35 U.S.C. § 101 would be defeated if a patent applicant is able to evade a § 101 rejection of a pure mathematical algorithm by a nominal claim to structure.

Wednesday, April 22, 2009

New Poll Question

"Is the BPAI being consistent in their application of Bilski?"

Please vote to the right.

Tuesday, April 21, 2009

Webinar on Bilski Strategies

I am leading a web cast on May 7, 2009 that focuses on some strategies for dealing with Bilski.

Details can be found here: "Beating Bilski: Strategies for Protecting 'Process' and 'Software' Innovations, from the Celesq®-West IP Master Series (1938IP)"

A Busy Friday

Last Friday, April 17, 2009, Dale M. Shaw Chief Appeals Administrator, remanded six cases that had received Docketing Notices back to their respective Examiner.

Each of the decisions includes language similar to the following:
Claims X, Y, and Z of the instant application are set forth as method claims that may not fall with one of the four statutory categories of invention recited in 35 U.S.C. § 101. On May 15, 2008, the Deputy Commissioner for Patent Examining Policy, John J. Love, issued a memorandum entitled “Clarification of “Processes” under 35 U.S.C. § 101.” This memorandum is further used in conjunction with the Interim Guidelines and the Manual of Patent Examining Procedure § 2106.IV.B, when determining whether a claimed invention falls within a statutory category of invention. See In re Bilski, 545 F.3d 943 (Fed. Cir. 2008)(en banc). Thus, there is a question as to whether claims X, Y, and Z meet the requirements of being a patent eligible process under 35 U.S.C. § 101.
It is interesting to note that the decision do not make reference to the post-Bilski memo of January 7, 2009. The watchdog posted a link to this January memo here: Bilski Guidelines Post

Could this signal a new trend from the BPAI?

If you would like .pdfs of the decisions, feel free to email me and I will send them along.

Saturday, April 11, 2009

A Data Packet is Not Patentable

Ex parte Michael J. Pizzo et al.
Decided: March 23, 2009

Not surprising, the BPAI held a claim directed a data packet transmitted between two computer components was not patentable subject matter. The Board relied on Nuitjen.

Claim 57 of Pizzo's application recited:
A data packet transmitted between two or more computer components that facilitate database query registration, database change detection and database change notification comprising:

database query registration information, associated with a registered database query, stored in a queue, and employed to construct and transmit a change message utilized to route a database change notification.
The Examiner reject the claim under 101. The Board relied on Nuitjen and affirmed stating simply that:
Claim 57 is directed to a “data packet transmitted between two or more computer components.” We construe the “transmitted” data packet to encompass a signal which is not subject matter patentable under 35 U.S.C. § 101.
It should come as no surprise by now that unless your claim is directed to one of the four statutory categories the BPAI will take exception.

Processor "Operable" to Peform a Function Render a System Claim Indefinite

Ex parte Craig Prouse
Decided: March 19, 2009

The practice of claiming a structure and then reciting what it is "operable" to do in a system claim may need to be revised in light of the reasoning in this decision.

Prouse's appeal focused on overcoming a 102(b) rejection of certain pending claims. Claim 1 recited:
1. A system in an electronic device for emitting light from a light-emitting diode (LED) at a variable brightness, comprising:

a waveform generator for generating an LED signal waveform comprised of a plurality of LED signal values; and

a processing unit operable to determine a scaling value for one or more LED signal values in the plurality of LED signal values, wherein the scaling value scales the one or more LED signal values based upon a percentage of a particular LED brightness.
The BPAI stated that "speculation and conjecture must be utilized by us and by the artisan inasmuch as independent claim 1 on appeal does not adequately reflect what the disclosed invention is." In analyzing the claims, the Board compared the "processing unit operable to determine" against the method claim that positively recited determining the scaling values. They stated:
In direct contrast to the positive statement of determining in independent claim 9, a processing unit is merely recited in independent claim 1 to be “operable to determine a scaling value.” Thus, it is merely capable of performing the recited or desired function of determining a scaling value. In other words, there is no present tense, positively recited determination of a scaling value in claim 1. Thus, since the scaling values are not actually determined, they cannot be used to scale the LED values as recited in the claim. This situation clearly renders the entire subject matter of independent claim 1 and its respective dependent claims 5-8 indefinite within the second paragraph of 35 U.S.C. § 112.
In view of the above, the Board reversed the Examiner's anticipation rejection of claims 1 and 9 and those claims depending from the independent claims. However, the Board issued a new ground of rejection with respect to claim 1 under the second paragraph of 35 U.S.C. § 112.

Is it time to rethink the practice of claiming "circuitry operable" to perform a certain function?

Is there a difference if the circuitry were "configured to" perform that function?

Wednesday, April 8, 2009

Where's the 101 rejection?

Ex Parte Sudesh Kamath, Tyson Hom, and Allen Lee
Decided: March 18, 2009

This is the first decision from Technology Center 3600 to appear on the Watchdog. Technology Center 3600 deals with "Business Method" patents. I find it notable that there is no discussion of 101 and the Board did not issue a new 101 rejection. There is also some interesting discussion around "teaching away" that might be the subject of a later post.

The technology at issue is methods and systems for streamlining and simplifying the online ordering process while affording the customer and/or other authorized persons the convenience of modifying or canceling the order after the initial commitment to order the product has been made.

Claim 1 of the application at issue recites:
A computer-implemented method of processing an online purchase request from a customer to a vendor over a computer network, comprising the steps of:

receiving, over the computer network, a first online purchase request for a first item;

responsive to receiving the first online purchase request, providing a bifurcated order processing route that requests the customer to choose a first order processing route causing the first online purchase request to be processed according to an express processing procedure that requires no further input by the customer to execute the first online purchase request, the second order processing route causing the first online purchasing request to be placed in a shopping cart that allows one or more additional purchase requests for additional items to be placed therein, the second order processing route affording the customer an opportunity to cause execution of the first and any additional purchase requests placed in the shopping card to be processed according to the express ordering processing that requires no further input by the customer to execute, and

receiving from the customer a selection of the first order processing route or the second order processing route and processing the first online purchase request according to the customer’s selection.

The Examiner rejected this claim under 103. That was the issue on appeal. Surprisingly, there is no discussion of the "machine or transform" test.

I took a look at the application. Paragraph [0036] includes the following sentence: "[w]ithin the context of the present invention, a "shopping cart" is a metaphor for a software construct enabling a customer to aggregate his or her online purchases for immediate or a later purchase."

Based on some of the Board's previous decisions, doesn't such a definition raise some eyebrows?

Also interesting, when compared against some of the other Board decisions previously discussed, is Paragraph [0045], which states:
The present invention is related to the use of computing device 700 to process a customer purchase request. According to one embodiment, the processing may be carried out by one or more computing devices 700 in response to processor(s) 702 executing sequences of instructions contained in memory 704. Such instructions may be read into memory 704 from another computer-readable medium, such as data storage device 707 and/or from a remotely located server. Execution of the sequences of instructions contained in memory 704 causes processor(s) 702 to implement the functionality described above. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the present invention. Thus, the present invention is not limited to any specific combination of hardware circuitry and software.

One could argue, that claim 1 could be directed to a "software" per se embodiment, which some panels have rejected under 101.

Also, what about previous Board decisions that used the guidelines set forth in MPEP § 2106(IV)(C)(2)(2)(a), that state claims must be amended to recite solely statutory subject matter?