Decided: April 24, 2009
Although this isn't the first time that a panel has held an apparatus was not within the scope of 101, this decision caught my attention because it deals with the "mathematical algorithm" exception.
Greene's application was generally directed to methods and an apparatus that improve on existing Fast Fourier Transform (FFT) calculations. The claim 60 provides further details of the improvement. Dependent claim 61 also adds to the discussion. Both claims are reproduced below. Sorry, claim 60 is a bit long.
Claim 60. A computer system for performing a fast Fourier transform on N ordered inputs in n stages comprising:
one or more vector processors configured as a non-final stage calculating means for repetitively performing in-place butterfly calculations for n-1 stages;
the one or more vector processors further configured as a final stage calculating means for performing a final stage of butterfly calculations including:
a first loop means for performing a portion of the final stage butterfly calculations, the first loop means performing a set of butterfly calculations, and storing butterfly calculation outputs in shuffled order in place of the selected inputs to result in a correct ordering of transform outputs; and
a second loop means for performing a remaining portion of the final stage butterfly calculations, the second loop means performing two sets of butterfly calculations, and storing butterfly calculation outputs from a first one of the two sets of butterfly calculations in shuffled order in place of the inputs selected for a second one of the two sets of butterfly calculations and storing butterfly calculation outputs from the second one of the two sets of butterfly calculations in shuffled order in place of the inputs selected for the first one of the two sets of butterfly calculations to result in a correct ordering of transform outputs,
wherein the final stage calculating means performs all butterfly calculations as radix-4 butterflies having four inputs and four outputs, wherein N is a power of two, and wherein the non-final stage calculating means performs a first stage of radix-8 butterfly calculations followed by n-2 stages of radix-4 butterfly calculations,
wherein the computer system produces the correct ordering of transform outputs with no need to perform an additional bit-reversal ordering pass.
Claim 61. The computer system of claim 60, wherein the non-final and final stage calculating means include a four-fold single instruction multiple data (SIMD) processor for performing four radix-4 butterfly calculations at a time.
The Examiner rejected these claims under 101 using pre-Bilski analysis. Throughout the prosecution, the applicant argued that the claim was patent eligible because it was directed to a machine. For example, he argued that claim 60 “defines a computer system that includes specific hardware structures, namely, vector processors. Moreover, it defines those structures in connection with means, (implemented in software) namely, the first loop means, second loop means, non-final stage calculating means, and final stage calculating means that are implemented, in the specification, in software."
It its analysis, the panel recognized that these claims were distinguishable from the method or process claims considered by the court in Bilski. The panel found that the preamble of independent claim 60 positively recites a computer system which is supported in the language found in the body of the claim. As such, the panel determined the claimed “computer system” was an apparatus which executes a software program.
With that in mind, the panel phrased the question before them as: "whether the 'mathematical algorithm' exception applies to an apparatus claim where the practical result of granting such a claim would preempt substantially all uses of a fundamental principle."
As you can guess, the Board found the claim did not fall withing the scope of 101.
The Board that these claims merely implement an optimized Fast Fourier Transform on a conventional computer system that includes one or more conventional vector processors. As claimed, we find the transform output results of the FFT calculation are not used for any practical purpose or inventive application whatsoever.
Further, the Board reasoned that without the recited conventional hardware elements, Appellant’s claim would be non-statutory under 35 U.S.C. § 101 as being directed to an abstract idea and/or a fundamental principal (i.e., a mathematical algorithm). Therefore, the question that remains is whether drafting an invention in a different statutory category (i.e., as a conventional apparatus or machine) is all that is necessary to overcome a § 101 rejection of a pure mathematical algorithm, particularly in view of the Federal Circuit’s recent discussion of Benson, stating that a computer-implemented method is not patent-eligible if the mathematical algorithm has no other use than operating on a digital computer and would preempt the fundamental principle since all uses of the algorithm are still covered by the claim.
In the end, the Board stated that merely adding a nominal recitation of conventional computer hardware in a claim otherwise directed to a pure mathematical algorithm is merely an exercise in claim drafting that cannot, by itself, render the claim statutory. The panel also said that it was their reasoned view that to hold otherwise would exalt form over substance and the practical effect would be a patent on the mathematical algorithm itself. The Board also said that the purpose of 35 U.S.C. § 101 would be defeated if a patent applicant is able to evade a § 101 rejection of a pure mathematical algorithm by a nominal claim to structure.